1. Field of the Invention
The present invention relates to a dual AAL1 device and a synchronization method used therewith and particularly relates to a synchronization method for the operation status between the act system and the standby system when an AAL1 (ATM Adaptation Layer Type 1) device to convert the STM (Synchronous Transfer Mode) data into ATM (Asynchronous Transfer Mode) cells has a dual configuration consisting of an act system (Current operation system) and a standby system (Reserved system).
2. Description of the Related Art
Conventionally, the STM data input to an AAL1 device to convert the STM data into ATM cells has the structure as shown in FIG. 10. As shown in FIG. 10, the STM data is given by time division multiplexing, where the channel is identified by the time position in the frame, and transferred for each time slot (TS; 1 TS=1 octet).
Further, an ATM cell converted by the above AAL1 device has the structure as shown in FIGS. 11 to 14. FIG. 11 shows a format of the SAR (Segmentation and Reassembly) sublayer. The ATM cell payload of 48 octets as a whole represents an SAR-PDU (SAR Protocol Data Unit). The first octet of the SAR-PDU is allocated to the SAR-PDU header and the remaining 47 octets are the SAR-PDU payload.
FIG. 12 shows a format of the SAR-PDU header and FIG. 13 shows a non-P format and FIG. 14 shows a P format. In FIG. 12, the first 4 bits of the SAR-PDU header are called “SN” (Sequence Number) and the latter 4 bits are called “SNP” (Sequence Number Protection).
The bits of the SAR-PDU header are used as follows: CSI (Convergence Sublayer Indication) is the bit used by the CS (Convergence Sublayer) and the utilization method differs for each CS.
The SC (Sequence Count) is the number indicating the order of the cell (which ranges from 0 to 7) and is given by the CS. The CRC (Cyclic Redundancy Check=Error correction detection code) and the P (Parity) are inspection bits for error control of the SAR-PDU header. By combining the CRC and the P, any error in the SAR-PDU header can be corrected or detected.
The structure of the ATM cell as shown in FIGS. 11 to 14 is designed so that it can support transfer of the STM signal frame structure to the receiver when required and the protocol for the structured data transfer is specified. In this case, as shown in FIG. 14, a pointer (which ranges from 0 to 93) is inserted to the cell to clearly indicate the first time slot of the STM data frame.
The pointer is inserted to the beginning of the SAR-PDU payload. The cells to which the pointer can be inserted are limited to those with even SC. The pointer is inserted once for one cycle of SC (0 to 7) and causes the CSI bit to be “1”. The cell structure to which the pointer is thus inserted is called the P format and, as shown in FIG. 13, the cell structure to which the pointer is not inserted is called the non-P format. In addition, the case without using the protocol for the structured data transfer is called the UDT (Unstructured Data Transfer) and the case using the structured data transfer protocol is called the SDT (Structured Data Transfer).
The functional blocks in an ATM switch for the ATM network have dual redundant configurations to assure a high reliability with confounding among the functional blocks. A dual-structure functional block uses one set of equipment as the act system and the other set of equipment as the standby system. It may be sometimes necessary to switch between the equipment serving as the act system and the equipment serving as the standby system for maintenance requirement.
If the timing to form ATM cells is not synchronized in the AAL1 device with the dual configuration, there will be phase differences between the payload of the cells output from the AAL1 device of the act system and that of the cells output from the AAL1 device of the standby system as shown in FIG. 15. This may result in lack or redundancy of data in system switching processing.
Japanese Patent Application Laid-open Print (Kokai) No. Heisei 9-55752 discloses a synchronization method for a dual AAL1 device to enable switching between the equipment serving as the act system and the equipment serving as the standby system without causing any lack or redundancy of information or other momentary shutdown.
The dual AAL1 device as described in the above patent application comprises inter-system signal lines connecting the act system AAL1 device and the standby system AAL1 device as well as a cell assembly buffer for one or more unit of channels provided for each system.
For synchronization, the cell assembly buffer number to execute synchronization is notified from the act system AAL1 device to the standby system AAL1 device by each unit of cell assembly buffer via the intersystem signal line at the timing when the storage data in the cell assembly buffer is the final octet of the SAR-PDU payload, i.e. the time slot input to the cell assembly buffer next is the first data of the SAR-PDU payload and when the SC of the SAR-PDU header becomes the predetermined value (“0”, for example).
Upon receipt of such notice, the standby system AAL1 device starts STM data taking into the cell assembly buffer starting from the applicable time slot of the next STM frame and thereby has the output ATM cell of the act system AAL1 device coincide with the output ATM cell of the standby system AAL1 device. By conducting the same processing for all channels one by one, the act system AAL1 device and the standby system AAL1 device are synchronized.
As described above, this method is characterized by that the cell forming is not started until the timing when a particular time slot of the STM frame can be allocated from the first octet of the SAR-PDU payload section having the predetermined SC value (“0” for example) for the SAR-PDU header. By this method, the cell forming statuses of the act system and the standby system can be made identical without causing momentary shutdown of the STM signal and, without any loss or redundancy of data, switching between the act system and the standby system can be achieved.
The conventional dual AAL1 device as described above waits for the timing when the particular time slot of the STM frame can be allocated from the first octet of the SAR-PDU payload section having the predetermined SC (“0”, for example) for the SAR-PDU header to start cell forming and it takes time to synchronize the standby system AAL1 device.
In addition, the conventional dual AAL1 device waits for the timing when the particular time slot of the STM frame can be allocated from the first octet of the SAR-PDU payload section having the predetermined SC (“0”, for example) for the SAR-PDU header to start cell forming and the frame cycle where the standby system AAL1 device can be synchronized varies depending on the time slot count in one channel of the STM data.
Details of these drawbacks are described below with referring to FIGS. 16 and 17. FIGS. 16 and 17 show the SAR-PDU payload extracted and laid out for every cycle (0 to 7) of for the SAR-PDU header. The section surrounded by a thick line shows the data for the same frame.
Suppose that a particular time slot of the STM frame is the first time slot of the frame and the first time slot of the frame is allocated from the first octet of the SAR-PDU payload having “0” for the SC of the SAR-PDU header. The frame cycle enabling allocation of the first time slot of the frame to the first octet of the SAR-PDU payload in the ATM cell having “0” as the SC is represented by “the least common multiple for the octet count of the SAR-PDU payload in one cycle of SC and the time slot count in one channel within one frame of the STM data divided by the time slot count in one channel within one frame of the STM data”.
In other words, different time slot counts in one channel within one frame of the STM data result in different frame cycles to enable allocating the first time slot of the frame to the first octet of the SAR-PDU payload in the ATM cell having “0” as the SC.
FIG. 16 shows the allocation to the ATM cell when the time slot count in one channel within one frame of the STM data is 470 (data for ten SAR-PDU payloads). Since the octet count in the SAR-PDU payload for one SC cycle is 376 octets and the time slot count in one frame of the STM data is 470, the least common multiple for them is 1880. When 1880 is divided by 470, the time slot count in one channel within one frame of the STM data, the quotient is 4.
Specifically, as shown in FIG. 16, the frame cycle in which the first time slot of a frame can be allocated to the first octet of the SAR-PDU payload of the ATM cell having “0” as SC is 4.
FIG. 17 shows the allocation to the ATM cell when the time slot count in one channel within one frame of the STM data is 423 (data for nine SAR-PDU payloads). Since the octet count in the SAR-PDU payload for one SC cycle is 376 octets and the time slot count in one frame of the STM data is 423, the least common multiple for them is 3384. When 3384 is divided by 423, the time slot count in one frame of the STM data, the quotient is 8.
Specifically, as shown in FIG. 17, the frame cycle in which the first time slot of a frame can be allocated to the first octet of the SAR-PDU payload of the ATM cell having “0” for is 8.
As described above, depending on the time slot count in one channel within one frame of the STM data, the frame cycle in which a particular time slot of a frame can be allocated from the first octet of the SAR-PDU payload section having the predetermined SC (“0”, for example) for the SAR-PDU header varies. Thus, depending on the time slot count in one channel within one frame of the STM data, the frame cycle in which a particular time slot of a frame can be allocated from the first octet of the SAR-PDU payload section having the predetermined SC (“0”, for example) for the SAR-PDU header may have several hundreds of frames. It takes time to synchronize the standby system AAL1 device.